1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a spare memory cell for replacing a defective memory cell
2. Description of the Background Art
For a semiconductor memory device which executes data storage, various data storage formats are employed to store data in memory cells. For example, there is provided a semiconductor memory device constituted so that the pass current of each memory cell changes according to data stored in the memory cell when the memory cell is accessed. In the semiconductor memory device of this type, the data stored in a selected memory cell is read in accordance with the comparison between the pass current of the selected memory cell to be accessed and a preset reference current. As semiconductor memory devices having such memory cells, attention is being paid to an MRAM Magnetic Random Access Memory) device capable of executing the storage of nonvolatile data with low power consumption.
Recently, in particular, it has been made public that the performance of an MRAM device dramatically-advances by employing thin film magnetic elements using MTJs (Magnetic Tunnel Junctions) as memory cells. The MRAM device which includes memory cells each having the MTJs is disclosed, for example, in the following technical documents:
Roy Scheuerlein and six others, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, February 2000, TA7.2, pp. 94-95, 128-129 and 409.
M. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, February 2000, TA7.3, pp. 96-97.
FIG. 18 is a schematic diagram showing a configuration of a memory cell which has a tunnel junction (hereinafter, also simply referred to as “MTJ memory cell”).
With reference to FIG. 18, the MTJ memory cell includes a tunneling magneto-resistance element TMR having electric resistance which changes in accordance with the data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is connected in series to tunneling magneto-resistance element TMR between a write bit line WBL and a read bit line RBL. As access transistor ATR, a field effect transistor formed on a semiconductor substrate is typically employed.
For the MTJ memory cell, write bit line WBL and write digit line WDL each for carrying data write currents in different directions during data write, a word line WL for instructing data read, and read bit line RBL receiving the supply of the data read currents are provided. During data read, in response to turning on access transistor ATR, tunneling magneto-resistance element TMR is electrically coupled between write bit line WBL set at a ground voltage GND and read bit line RBL.
FIG. 19 is a conceptual view for describing a data write operation for writing data to the MTJ memory cell.
With reference to FIG. 19, tunneling magneto-resistance element TMR includes a ferromagnetic material layer FL which has a fixed constant magnetic direction (hereinafter, also simply referred to as “fixed magnetic layer”) and a ferromagnetic material layer VL which is magnetized in a direction according to a magnetic field applied from externally (hereinafter, also simply referred to as “free magnetic layer”). A tunneling barrier (tunneling film) TB formed from an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction or the opposite direction to that of fixed magnetic layer FL in accordance with the level of stored data to be written. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.
The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetic direction of fixed magnetic layer FL and that of free magnetic layer VL. Specifically, if the magnetic direction of fixed magnetic layer FL is parallel to that of free magnetic layer VL, the electric resistance value of tunneling magneto-resistance element TMR is a minimum value Rmin. If these magnetic directions are opposite (non-parallel) to each other, the electric resistance value of tunneling magneto-resistance element TMR is a maximum value Rmax.
During data write, word line WL is deactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL is carried to each of bit line BL and write digit line WDL in a direction according to the level of the write data.
FIG. 20 is a conceptual view for describing the relationship between the data write current and the magnetic direction of a tunneling magneto-resistance element during data write.
With reference to FIG. 20, the horizontal axis indicates a magnetic field applied in an easy axis (EA: Easy Axis) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. The vertical axis H(HA) indicates a magnetic field applied in a hard axis (HA: Hard Axis) direction in free magnetic layer VL. Magnetic fields H(EA) and H(HA) correspond to two magnetic fields generated by currents carried to bit line BL and write digit line WDL, respectively.
In the MTJ memory cell, the fixed magnetic direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized in a direction parallel or non-parallel (opposite) to fixed magnetic layer FL along the easy axis direction in accordance with the level of stored data (“1” or “0”). The MTJ memory cell can store 1-bit data (“1” and “0”) corresponding to the two magnetic directions of free magnetic layer VL.
The magnetic direction of free magnetic layer VL can be rewritten only when the sum of magnetic fields H(EA) and H(HA) applied to free magnetic layer VL reaches a region outside of an asteroid characteristic line shown in FIG. 20. In other words, when the data write magnetic field applied to free magnetic layer VL has an intensity corresponding to the region inside of the asteroid characteristic line, the magnetic direction of free magnetic layer VL has no change.
As shown in the asteroid characteristic line, if a magnetic field in the hard axis direction is applied to free magnetic layer VL, it is possible to decrease a magnetc threshold necessary to change the magnetic direction of free magnetic layer VL along the easy axis.
If operation points during data write are designed as shown in the example of FIG. 20, the data write magnetic field in the easy axis direction is designed so as to have an intensity of HWR in the MTJ memory cell to which the data is to be written. That is, the value of the data write current carried to each of bit line BL and write digit line WDL is designed so as to obtain this data write magnetic field HWR. Generally, data write magnetic field HWR is expressed by the sum of a switching magnetic field HSW necessary to change over a magnetic direction and a margin ΔH, i.e., HWR=HSR+ΔH.
In order to rewrite the stored data of the MTJ memory cell, i.e., to rewrite the magnetic direction of tunneling magneto-resistance element TMR, it is necessary to carry a data write current at predetermined level or higher to each of write digit line WDL and bit line BL. Thereby, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in the direction parallel or opposite (non-parallel) to that of fixed magnetic layer FL in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetic direction which is written to tunneling magneto-resistance element TMR once, i.e., the stored data of the MTJ memory cell is held in a nonvolatile manner until new data is written.
FIG. 21 is a conceptual view for describing a data read operation for reading data from the MTJ memory cell.
With reference to FIG. 21, during data read, access transistor ATR is turned on in response to the activation of word line WL. Write bit line WBL is set at ground voltage GND. As a result, tunneling magneto-resistance element TMR is electrically coupled to read bit line RBL while being pulled down at ground voltage GND.
In this state, if read bit line RBL is pulled up at a predetermined voltage, a memory cell current Icell according to the electric resistance of tunneling magneto-resistance element TMR, i.e., according to the level of the stored data in the MTJ memory cell, passes through a current path which includes read bit line RBL and tunneling magneto-resistance element TMR. By comparing this memory cell current Icell with a predetermined current, for example, it is possible to read the data stored in the MTJ memory cell.
As described above, the electric resistance of tunneling magneto-resistance element TMR changes according to the magnetic direction which can be rewritten by the data write magnetic field applied thereto. Therefore, if electric resistance values Rmax and Rmin of tunneling magneto-resistance element TMR are made to correspond to the levels (“1” and “0”) of the stored data, respectively, it is possible to store nonvolatile data.
An MRAM of 1 transistor-1 MTJ element type as shown in FIG. 18, however, sometimes causes a malfunction depending on the finished states of memory cell elements. Due to this, redundant memory cells are often provided in preparation for an instance in which a failure such as a malfunction generates to a normal memory cell. If a defective memory cell is discovered and this defective memory cell is replaced by a spare memory cell, a chip which has been determined to be a failure chip once can be relieved.
Nevertheless, the spare memory cells are often provided in a portion peripheral of a memory cell array. If the spare memory cells are located in such a peripheral portion, the finished dimensions of elements tend to exhibit a wide range of variation compared with the central portion of the memory cell array. If a spare memory cell is defective, a chip cannot be relieved even by replacing a defective memory cell by the spare memory cell.